Kev lees paub kuj tuaj yeem nkag mus rau qhov hloov pauv zoo li qub tau hais tseg hauv cov chav kawm; Txawm li cas los xij, kev nkag mus rau dynamic lossis rand variables yog txhaum cai. Concurrent assertions yog txhaum cai nyob rau hauv cov chav kawm, tab sis muaj peev xwm tsuas yog sau nyob rau hauv modules, SystemVerilog interfaces, thiab SystemVerilog checkers2.
Dab tsi yog qhov kev lees paub SystemVerilog?
Hauv SystemVerilog muaj ob hom kev lees paub: tam sim (tsim) thiab concurrent (ssert property). Cov nqe lus them nqi (cov khoom ntiag tug) yog concurrent thiab muaj tib syntax raws li concurrent assertions, assume khoom nqe lus.
Qhov kev lees paub SystemVerilog yog dab tsi?
SystemVerilog Assertions (SVA) yog tseem ceeb yog hom lus tsim uas muab txoj hauv kev muaj zog los sau cov kev txwv, checkers thiab npog cov ntsiab lus rau koj tus qauv. Nws cia koj qhia cov cai (piv txwv li, cov kab lus Askiv) hauv cov qauv tsim hauv SystemVerilog hom uas cov cuab yeej tuaj yeem nkag siab.
Yuav ua li cas yog ib ntus raws li siv hauv kev sau ntawv SystemVerilog kev lees paub?
Boolean nthuav qhia cov xwm txheej uas ntsuas ntau lub sijhawm uas cuam tshuam nrog ib zaug / ntau lub moos. SVA muab lo lus tseem ceeb los sawv cev cov xwm txheej no hu ua "ib ntus".
Vim li cas peb thiaj xav tau kev lees paub hauv SV?
SystemVerilog Assertions (SVA) tsim ib qho tseem ceeb ntawm SystemVerilog, thiab xws li tej zaum yuav raug nkag rau hauv Verilog thiab VHDL tsim ntws uas twb muaj lawm. Cov lus qhia feem ntau yog siv los ntsuas tus cwj pwm ntawm tus qauv.
